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NCV7708 Double Hex Driver
The NCV7708 is a fully protected Hex-Half Bridge-Driver designed specifically for automotive and industrial motion control applications. The six low and high side drivers are freely configurable and can be controlled separately. This allows for high side, low side, and H-Bridge control. H-Bridge control provides forward, reverse, brake, and high impedance states. The drivers are controlled via a standard SPI interface.
Features
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* * * * * * * * * * * * * *
Ultra Low Quiescent Current Sleep Mode Six Independent High-Side and Six independent Low-Side Drivers Integrated Freewheeling Protection (LS and HS) Configurable as H-Bridge Drivers 0.5 A Continuous (1 A peak) Current RDSon = 0.8 W (typ) 5 MHz SPI Control Compliance with 5 V and 3.3 V Systems Overvoltage Lockout Undervoltage Lockout Fault Reporting Current Limit Over-temperature Protection Pb-Free Packages are Available*
SOIC-28 DW SUFFIX CASE 751F
MARKING DIAGRAM
NCV7708 AWLYYWWG
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
1 OUTL5 OUTH5 OUTH4 OUTL4 VS2 GND GND GND GND VS1 OUTL3 OUTH3 OUTH2 OUTL2 OUTH6 OUTL6 SI SCLK CSB GND GND GND GND VCC SO EN OUTL1 OUTH1
Typical Applications
* Automotive * Industrial
ORDERING INFORMATION
Device NCV7708DW NCV7708DWG NCV7708DWR2 Package SOIC-28W SOIC-28W (Pb-Free) Shipping 26 Units/Rail 26 Units/Rail
SOIC-28W 1000/Tape & Reel
NCV7708DWR2G SOIC-28W 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
October, 2006 - Rev. 1
Publication Order Number: NCV7708/D
NCV7708
VS1 DRIVE 1 High-Side Driver Waveshaping
VS EN ENABLE CP Charge Pump Control Logic BIAS POR Fault Detect SPI Control SO Fault
VS
OUTH1
VCC
Low-Side Driver Waveshaping Under-load Overcurrent Thermal Warning/Shutdown
OUTL1
SI
SPI
SCLK
16 Bit Logic and Latch VS
OUTH2 DRIVE 2
CSB CP
OUTL2
VS DRIVE 3 CP
OUTH3
OUTL3
VS1 Undervoltage Lockout VS2 CP VS DRIVE 4 OUTL4 OUTH4
VS1 Overvoltage Lockout VS2
VS DRIVE 5 CP
OUTH5
OUTL5
VS DRIVE 6 CP
OUTH6
OUTL6
GND
VS2
Figure 1. Block Diagram
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NCV7708
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol OUTL5 OUTH5 OUTH4 OUTL4 VS2 GND GND GND GND VS1 OUTL3 OUTH3 OUTH2 OUTL2 OUTH1 OUTL1 EN SO VCC GND GND GND GND CSB SCLK SI OUTL6 OUTH6 Description Output Low Side 5. Open drain output driver with internal reverse diode. Output High Side 5. Open source output driver with internal reverse diode. Drain connected to VS2. Output High Side 4. Open source output driver with internal reverse diode. Drain connected to VS2. Output Low Side 4. Open drain output driver with internal reverse diode. Voltage Power Supply input for the High-Side Output Drivers 4, 5, and 6. Ground. Ground. Ground. Ground. Voltage Power Supply input for the High-Side Output Drivers 1, 2, and 3, All Six Low-Side Pre Drivers, and All Six Charge Pumps. Output Low Side 3. Open drain output driver with internal reverse diode. Output High Side 3. Open source output driver with internal reverse diode. Drain connected to VS1. Output High Side 2. Open source output driver with internal reverse diode. Drain connected to VS1. Output Low Side 2. Open drain output driver with internal reverse diode. Output High Side 1. Open source output driver with internal reverse diode. Drain connected to VS1. Output Low Side 1. Open drain output driver with internal reverse diode. Enable. Input high wakes the IC up from a sleep mode. Serial Output. 16 bit serial communications output. Power supply input for Logic. Ground. Ground. Ground. Ground. Chip Select Bar. Active low serial port operation. Serial Clock. Clock input for use with SPI communication. Serial Input. 16 bit serial communications input. Output Low Side 6. Open drain output driver with internal reverse diode. Output High Side 6. Open source output driver with internal reverse diode. Drain connected to VS2.
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NCV7708
MAXIMUM RATINGS
Rating Power Supply Voltage (VS1, VS2) (DC) (AC), t < 500 ms, Ivsx > -2 A Output Pin OUTHx (DC) (AC - inductive clamping) Output Pin OUTLx (DC) (AC), t < 500 ms, IOUTLx > -2 A External Clamp Voltage (Note 3) Pin Voltage (Logic Input pins, SI, SCLK, CSB, SO, EN, VCC) Output Current (OUTL1, OUTL2, OUTL3, OUTL4, OUTL5, OUTL6, OUTH1, OUTH2, OUTH3, OUTH4, OUTH5, OUTH6) (DC) Vds = 12 V (DC) Vds = 20 V (DC) Vds = 40 V (AC) Vds = 12 V, (50 ms pulse, 1 s period) (AC) Vds = 20 V, (50 ms pulse, 1 s period) (AC) Vds = 40 V, (50 ms pulse, 1 s period) Electrostatic Discharge, Human Body Model, VS1, VS2, OUTx Electrostatic Discharge, Human Body Model, all other pins Electrostatic Discharge, Machine Model Operating Junction Temperature Storage Temperature Range Moisture Sensitivity Level MAX 235C Processing Value Unit V -0.3 to 40 -1.0 V -0.3 to 40 -8.0 V -0.3 to 34 -1.0 48 -0.3 to 7.0 V A -1.5 to 1.5 -0.7 to 0.7 -0.25 to 0.25 -2.0 to 2.0 -0.9 to 0.9 -0.3 to 0.3 4.0 2.0 200 -40 to 150 -55 to 150 3 kV kV V C C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Thermal Parameters SOIC 28-pin Package min-pad board (Note 1) Junction-to-Lead (psi-JL8, YJL8) or Pins 6-9, 20-23 Junction-to-Ambient (RqJA, qJA) 1. 1-oz copper, 240 copper area, 0.062 thick FR4. 2. 1-oz copper, 986 copper area, 0.062 thick FR4. 3. OUTLx must be protected against flyback voltages that exceed 48 V. mm2 mm2 10 73 1-pad board (Note 2) 11 56 C/W C/W Test Conditions Typical Value
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NCV7708
ELECTRICAL CHARACTERISTICS
(-40C < TJ < 150C, 5.5 V < VSx < 40 V, 3 V < VCC < 5.25 V, EN = VCC, unless otherwise specified) Characteristic GENERAL Supply Current (VS1 + VS2) Sleep Mode Supply Current (VS1) Active Mode Supply Current (VS2) Active Mode Supply Current (VCC) - Sleep Mode (Note 5) Supply Current (VCC) - Active Mode VCC Power-On-Reset Threshold VSx Undervoltage Detection Threshold VSx Undervoltage Detection Hysteresis VSx Overvoltage Detection Threshold VSx Overvoltage Detection Hysteresis Thermal Warning (Note 4) Thermal Warning Hysteresis (Note 4) Thermal Shutdown (Note 4) Ratio of Thermal Shutdown to Thermal Warning (Note 4) OUTPUTS Output High RDSon (source) Iout = -500 mA 8 V < Vs < 40 V 8 V < Vs < 40 V, T = 25C 5.5 V < Vs 8 V 5.5 V < Vs 8 V, T = 25C Iout = 500 mA 8 V < Vs < 40 V 8 V < Vs < 40 V, T = 25C 5.5 V < Vs 8 V 5.5 V < Vs 8 V, T = 25C OUTH(1-6) = 0 V, VSx = 40 V, VCC = 5 V OUTH(1-6) = 0 V, T = 25C, VCC = 5 V OUTL(1-6) = 34 V, VCC = 5 V OUTL(1-6) = 34 V, VCC = 5 V, T = 25C VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V W - - - - - 0.8 - 2.0 2.0 1.3 4.0 - W - - - - -5.0 -1.0 - - -1.9 -5.0 1.0 10 10 - 0.8 - 2.0 - - - - -1.45 -3.0 1.45 25 25 2.0 1.2 4.0 - - - 5.0 1.0 -1.0 -2.0 1.9 50 50 mA mA VSx increasing VSx decreasing VS1 = VS2 = 13.2 V, VCC = CSB = 5 V, EN = SI = SCLK = 0 V EN = VCC, 5.5 V < VSx < 35 V No Load EN = VCC, 5.5 V < VSx < 35 V No Load CSB = VCC, EN = SI = SCLK = 0 V (-40C to 85C) EN = CSB = VCC, SI = SCLK = 0 V - 1.0 5.0 mA Test Conditions Min Typ Max Unit
-
2.0
4.0
mA
- - - 2.60 4.2 100 35.0 1.5 120 - 155 1.05
0.5 1.0 1.5 2.80 4.6 - 37.5 3.5 145 30 175 1.20
1.0 2.5 3.0 3.00 5.1 400 40.0 5.5 170 - 195 -
mA mA mA V V mV V V C C C -
Output Low RDSon (sink)
Source Leakage Current
Sink Leakage Current
Overcurrent Shutdown Threshold (OUTHx) Current Limit (OUTHx) Overcurrent Shutdown Threshold (OUTLx) Overcurrent Shutdown Delay Time - Source Overcurrent Shutdown Delay Time - Sink 4. 5. 6. 7.
A A A ms
Thermal characteristics are not subject to production test. Production tested @ -40C, 125C. Refer to graph 6 for VCC sleep current vs. temperature. Refer to "Typical High-Side Negative Clamp Voltage Chart," Figure 5 Not production tested.
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NCV7708
ELECTRICAL CHARACTERISTICS
(-40C < TJ < 150C, 5.5 V < VSx < 40 V, 3 V < VCC < 5.25 V, EN = VCC, unless otherwise specified) Characteristic OUTPUTS Current Limit (OUTLx) Under Load Detection Threshold (OUTLx) Under Load Detection Threshold (OUTHx) Under Load Detection Delay Time High-Side Clamping Voltage Power Transistor Body Diode Forward Voltage Logic Inputs (EN, SI, SCLK, CSB) Input Threshold - High Input Threshold - Low Input Hysteresis Input Pulldown Current (EN, SI, SCLK) Sleep Mode (SI, SCLK) Input Pullup Current (CSB) Sleep Mode Input Capacitance (Note 7) Logic Output (SO) Output High Output Low Tri-state Leakage Tri-state Input Capacitance (Note 7) Timing Specifications High Side Turn On Time High Side Turn Off Time Low Side Turn On Time Low Side Turn Off Time High Side Rise Time High Side Fall Time Low Side Rise Time Low Side Fall Time Non-Overlap Time Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W Vs = 13.2 V, Rload = 25 W High Side Turn Off To Low Side Turn On Low Side Turn Off To High Side Turn On - - - - - - - - 1.5 7.5 3.0 6.5 2.0 4.0 2.0 1.0 1.0 - 13 6.0 13 5.0 8.0 3.0 2.0 3.0 - ms ms ms ms ms ms ms ms ms ms Iout = 1 mA Iout = -1.6 mA CSB = VCC, 0 V < SO < VCC CSB = VCC, 0 V < VCC < 5.25 V VCC - 1.0 - -10 - VCC - 0.7 0.2 - 10 - 0.4 10 15 V V mA pF EN = SI = SCLK = VCC EN = 0, SI = SCLK = VCC CSB = 0 V, EN = VCC EN = 0 V, VCC = 5 V - 30 100 5.0 10 -50 -100 - - - 300 10 50 -10 -50 10 70 - 600 50 100 -5.0 -10 15 %VCC VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V VCC = 5 V, Vsx = 13.2 V I(OUTHx) = -50 mA If = 500 mA 2.0 3.0 -15 200 3.0 8.0 -6.0 350 (Note 6) 0.9 5.0 15 -2.0 600 -0.7 1.3 A mA mA ms V V Test Conditions Min Typ Max Unit
mV mA mA
pF
Non-Overlap Time 4. 5. 6. 7.
2.5
-
-
Thermal characteristics are not subject to production test. Production tested @ -40C, 125C. Refer to graph 6 for VCC sleep current vs. temperature. Refer to "Typical High-Side Negative Clamp Voltage Chart," Figure 5 Not production tested.
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NCV7708
Serial Peripheral Interface
Characteristic SCLK Frequency SCLK Clock Period Maximum Input Capacitance (Note 8) SCLK High Time SCLK Low Time SCLK Setup Time SI Setup Time SI Hold Time CSB Setup Time CSB High Time (Note 9) SO enable after CSB falling edge SO disable after CSB rising edge SO Rise Time SO Fall Time SO Valid Time Cload = 40 pF Cload = 40 pF SCLK to SO 50% VCC = 5 V VCC = 3.3 V SI, SCLK - 1 2 3 4 11 12 5 6 7 8 9 - - 10 (VCC = 5 V) Conditions Timing Chart # Min - 200 500 - 85 85 85 85 50 50 100 100 200 - - - - - Typ - - - - - - - - - - - - - - - 10 10 20 Max 5.0 - - 12 - - - - - - - - - 50 50 25 25 50 Unit MHz ns pF ns ns ns ns ns ns ns ns ns ns ns ns
8. Not tested in production 9. This is the minimum time the user must wait between SPI commands.
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NCV7708
4 7
CSB 6 5 SCLK
3
1
2
CSB
SO
8
9
SI 12
SCLK 11 10
SO
Figure 2. SPI Timing Diagram
SPI Communication
Standard 16-bit communication has been implemented for the communication of this IC to turn drivers on and off, and to report faults. (Reference the SPI Communication Frame Format Diagram). The LSB (Least Significant Bit) is clocked in first. Communication is implemented as follows:
1. CSB goes low to allow serial data transfer. 2. A 16 bit word is clocked (SCLK) into the SI (serial input) pin. 3. CSB goes high to transfer the clocked in information to the data registers. (Note: SO is tristate when CSB is high.)
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NCV7708
CSB
SI
SRR
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6
OCD
ULD
OVLO
SCLK
SO
TW
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3 OUTL4 OUTH4 OUTL5 OUTH5 OUTL6 OUTH6
OLD
ULD
PSF
Figure 3. SPI Communication Frame Format
The table below defines the programming bits and diagnostic bits. Fault information is sequentially clocked out the SO pin of the NCV7708 as programming information is clocked into the SI pin of the device. Daisy chain
Input Data Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Description Over Voltage Lock Out Control (OVLO) Under Load Detection Shut Down Control (ULD) Over Current Detection Shut Down Control (OCD) OUTH6 OUTL6 OUTH5 OUTL5 OUTH4 OUTL4 OUTH3 OUTL3 OUTH2 OUTL2 OUTH1 OUTL1 Status Register Reset (SRR) Bit Status 0 = Disable 1 = Enable 0 = Disable 1 = Enable 0 = Disable 1 = Enable 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = No Reset 1 = Reset
communication between SPI compatible IC's is possible by connection of the serial output pin (SO) to the input of the sequential IC (SI).
Output Data Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Description Power Supply Fail Signal (OVLO or UVLO = PSF) Under Load Detect Signal (ULD) Over Load Detect Signal (OLD) OUTH6 OUTL6 OUTH5 OUTL5 OUTH4 OUTL4 OUTH3 OUTL3 OUTH2 OUTL2 OUTH1 OUTL1 Thermal Warning (TW) Bit Status 0 = No Fault 1 = Fault 0 = No Fault 1 = Fault 0 = No Fault 1 = Fault 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Off 1 = On 0 = Not in TW 1 = In TW
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NCV7708
DETAILED OPERATING DESCRIPTION
General
The NCV7708 Double Hex Driver provides drive capability for 3 independent H-Bridge configurations, or 6 High Side configurations with 6 Low Side configurations, or any combination of arrangements. Each output drive is characterized for a 500 mA load and has a typical 1.0 A surge capability (at 12 V). Strict adherence to integrated circuit die temperature is necessary. Maximum die temperature is 150C. This may limit the number of drivers enabled at one time. Output drive control and fault reporting is handled via the SPI (Serial Peripheral Interface) port. An Enable function (EN) provides a low quiescent sleep current mode when the device is not being utilized. No data is stored when the device is in sleep mode. A pull down current source is provided on the EN input to ensure the device is off if the input signal is lost. Pull down current sources are also provided on the SI and SCLK inputs. A pull up current source is provided for the CSB input for the same reason. A loss of signal pulls the CSB input high to stop any spurious signals into the SPI port.
Power Up/Down Control
initialized in the off (high impedance) condition, and will remain off regardless of the status of VCC. This allows power up sequencing of VCC, VS1, and VS2 up to the user. The voltage on VS1 and VS2 should be operated at the same potential. A built-in hysteresis on the under voltage threshold is included to prevent an unknown region on the power pins. After a device has powered up and the output drivers are allowed to turn on, the output drivers will not turn off until the voltage on the supply pins is reduced from the initial under voltage threshold, or if shut down by either a SPI command or a fault condition. Internal power-up circuitry on the logic supply pin supports a smooth turn on transition. VCC power up resets the internal logic such that all output drivers will be off as power is applied. Exceeding the under voltage lockout threshold on VCC allows information to be input through the SPI port for turn on control. Logic information remains intact over the entire VS1 and VS2 voltage range.
Current Limitation
An under voltage lockout circuit prevents the output drivers from turning on unintentionally. This control is provided by monitoring the voltages on the VS1, VS2, and VCC pins. Each analog power pin (VS1 or VS2) powers their respective output drivers (VS1 powers OUTH1, OUTH2, OUTH3, all 6 charge pumps and all 6 low side pre-drivers. VS2 powers OUTH4, OUTH5, and OUTH6). All drivers are
Over Current Detection Shut Down
OCD Input Bit 13 0 0 1 1 OUTx OCD Condition 0 1 0 1 Output Data Bit 13 Over Load Detect (OLD) Status 0 1 (Need SRR to reset) 0 1 (Need SRR to reset)
Input bit 13 (OCD) controls the action of driver shutoff during current limit. With a 0 for bit 13, there is no driver shutoff, and the drivers current limit at 3 A. With a 1 for input bit 13, the output drivers shut off when the shutdown threshold current is passed. Devices can be turned back on via the SPI port. Note: high currents could cause a high rise in die temperature. Devices will not turn on if the die temperature exceeds the thermal shutdown temperature.
OUTx Status Unchanged Unchanged Unchanged OUTx Latches Off (Need SRR to reset)
Current Limit of all Drivers 3A 3A 3A 3A
Under load Detection
The under-load detection is accomplished by monitoring the current from each output driver. A minimum load current (this is the maximum open circuit detection threshold) is required when the drivers are turned on. If the under-load circuit detection threshold has been crossed for more than
Under Load Detection Shut Down
ULD Input Bit 14 0 0 1 1 OUTx ULD Condition 0 1 0 1 Output Data Bit 14 Under Load Detect (ULD) Status 0 1 (Need SRR to reset) 0 1 (Need SRR to reset)
the under-load delay time, the bit indicator (output bit #14) for open circuit will be set to a 1. In addition, the offending driver will be turned off only if input bit 14 (ULD) is set to 1 (true).
OUTx Status Unchanged Unchanged Unchanged OUTx Latches Off (Need SRR to reset)
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NCV7708
Over Voltage Shutdown
Over voltage shutdown circuitry monitors the voltage on the VS1 and VS2 pins. When the Over-voltage Threshold voltage level has been breached on both or either one of the VSx supply inputs, output bit 15 will be set and, if input bit 15 (OVLO) is set to 1, all outputs will turn off. Turn on/off
Over Voltage Lock Out (OVLO) Shut Down
OVLO Input Bit 15 0 0 1 1 VSx OVLO Condition 0 1 0 1 Output Data Bit 15 Power Supply Fail (PSF) Status 0 1 (Need SRR to reset) 0 1 (Need SRR to reset)
status is maintained in the logic circuitry. When proper input voltage levels are re-established, the programmed outputs will turn back on. Over-voltage shutdown can be disabled by using the SPI input bit 15 (OVLO = 0).
OUTx Status Unchanged Unchanged Unchanged All Outputs Off (Remain off until VSx is out of OVLO)
Thermal Shutdown
Six independent thermal shutdown circuits are featured (one common sensor for each HS and LS transistor pair). Each sensor has two levels, one to give a Thermal Warning (TW) and a higher one, Over Temperature, which will shut the drivers off. When the part reaches the temperature point of Thermal Warning, the output data bit 0 (TW) will be set to a 1, and the outputs will remain on. With one or more sensors detecting the over temperature level, all channels will be turned off simultaneously. All outputs will return to normal operation when the part thermally recovers (Thermal toggling), because the over temperature shutdown does not change the actual channel selection. The output data bit 0, Thermal Warning, will latch and remain set, even after cooling, and is reset by using a software command to input bit 0 (SRR). Since thermal warning precedes a thermal shutdown, software polling of this bit will allow for load
control and possible prevention of thermal shutdown conditions. Thermal warning information can be retrieved immediately without performing a complete SPI access cycle. Figure 4 below displays how this is accomplished. Bringing the CSB pin from a 1 to a 0 condition immediately displays the information on the output data bit 0, thermal warning, even in the absence of a SCLK signal. As the temperature of the NCV7708 changes from a condition from below the thermal warning threshold to above the thermal warning threshold, the state of the SO pin changes and this level is available immediately when the CSB goes to 0. A 0 on SO indicates there is no thermal warning, while a 1 indicates the IC is above the thermal warning threshold. This warning bit is reset by using the input data bit 0, SRR.
CSB
CSB
SCLK
SCLK
SO Tristate Level
TWH
SO
Tristate Level NTW
Thermal Warning High
No Thermal Warning
Figure 4. Access to Temperature warning information shows the thermal information is available immediately with activation of the CSB signal without having to toggle the SCLK line.
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NCV7708 Typical Operating Characteristics
-1.2 HIGH SIDE CURRENT (A) -1.0 -0.8 -0.6 -0.4 -0.2 0 0 -1.0 -2.0 -3.0 -4.0 HIGH SIDE PIN VOLTAGE (V) VCC SUPPLY CURRENT (mA) 4.0
3.0
2.0
1.0
0 -50
0
50 TJ, TEMPERATURE (C)
100
150
Figure 5. Typical High-side Negative Clamp Voltage vs. Reverse Current, Room Temperature Applications Drawing
Figure 6. VCC Sleep Supply Current vs. Temperature
The applications drawing below displays the range with which this part can drive a multitude of loads. The dotted line connecting the outputs exhibits the NCV7708 diversity.
+
1. H-Bridge Driver configuration 2. Low Side Driver 3. High Side Driver
VSx
OUTHx OUTLx 1 2
3
GND VSx M
OUTHx OUTLx
GND
Figure 7. Application Drawing
Any combination of motors and high side drivers can be designed in. This allows for flexibility in many systems.
H-Bridge Driver Configuration Overvoltage Clamping - Driving Inductive Loads
The NCV7708 has the flexibility of controlling each driver independently. When the device is set up in an H-Bridge configuration, the software design has to take care of avoiding simultaneous activation of connected HS and LS transistors. Resulting high shoot through currents could cause irreversible damage to the device.
To avoid excessive voltages when driving inductive loads in a single-side-mode (LS or HS switch, no freewheeling path), external clamping diodes for inductive turn off of the low side driver must be provided. The maximum clamp voltage is 48 V. Due to high power dissipation during clamping, the maximum energy capability of the driver transistor has to be considered.
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NCV7708
Thermal Model
Lead #1 Various copper areas used for heat spreading Package Construction With and Without Mold Compound Molded as 1/4 Symmetry
Active Area (red) Lead #8 (one of 8 thermal leads) 110 100 90 qJA (C/W) 80 70 60 50 40 0 100 200 300 400 500 600 700 800 900 1000 COPPER AREA (mm2) 2 oz 1 oz
Figure 8. qJA vs. Copper Spreader Area
100 Cu_Area = 239 mm2 1 oz 10 R(t) (C/W)
Cu_Area = 986 mm2 1 oz 1 S
1.0
0.1
0.01 0.000001 0.00001
0.0001
0.001
0.01 TIME (sec)
0.1
1.0
10
100
1000
Figure 9. SOIC 28-Lead Single Pulse Heating Curve
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NCV7708
100 D = 0.50 10 R(t) (C/W) D = 0.20 D = 0.10 D = 0.05 D = 0.01
1.0
0.1 Cu_Area = 986 mm2 1 oz 1 S 0.01 0.000001 0.00001 0.0001
0.001
0.01
0.1
1.0
10
100
1000
PULSE DURATION (sec)
Figure 10. SOIC 28-Lead Thermal Duty Cycle Curves on 1, Spreader Test Board
SOIC 28-lead Thermal RC Network Models
239 mm2 986 mm2 239 mm2 986 mm2 Cauer Network C's 2.68E-05 1.02E-04 2.82E-04 9.58E-04 2.72E-03 2.02E-03 2.93E-02 0.116 0.16 1 R's 0.048 0.115 0.352 0.777 0.599 1.677 2.968 6.424 6.940 53.503 C's 2.68E-05 1.02E-04 2.84E-04 9.73E-04 2.63E-03 1.95E-03 3.12E-02 0.091 0.21 1 R's 0.048 0.115 0.349 0.776 0.630 1.667 3.151 5.527 6.689 36.970 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Units W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C W-s/C Foster Network Tau 1.00E-06 1.00E-05 1.00E-04 5.00E-04 1.00E-03 1.00E-02 8.00E-02 4.00E-01 2.00E+00 6.00E+01 R's 2.84E-02 6.14E-02 1.94E-01 0.100 0.500 1.839 2.207 1.249 8.225 59.000 Tau 1.00E-06 1.00E-05 1.00E-04 5.00E-04 1.00E-03 1.00E-02 8.00E-02 4.00E-01 2.00E+00 5.50E+01 R's 2.84E-02 6.14E-02 1.94E-01 0.100 0.480 1.933 1.836 2.291 8.000 41.000 C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Cu Area Units sec sec sec sec sec sec sec sec sec sec
Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network are computed by the square root of time constant R(t) = 28.4 * sqrt(time(sec)). The constant is derived based on the active area of the device with silicon and epoxy at the interface of the heat generation.
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NCV7708
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Both Foster and Cauer networks can be easily implemented using
Junction R1 R2 R3
circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula:
n
R(t) +
i+1
Ri 1 * e *t
taui
Rn
C1
C2
C3
Cn Ambient (thermal ground)
Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values.
Figure 11. Grounded Capacitor Thermal Network ("Cauer" Ladder)
Junction R1 R2 R3 Rn
C1
C2
C3
Cn Ambient (thermal ground)
Each rung is exactly characterized by its RC-product time constant; amplitudes are the resistances.
Figure 12. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)
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15
NCV7708
PACKAGE DIMENSIONS
SOIC-28 WB CASE 751F-05 ISSUE G
-X- D
28
15
E -Y-
1 PIN 1 IDENT 14
H 0.25
M
Y
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBER PR5OTRUSION SHALL NOT BE 0.13 TOTATL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
A 0.10 G B 0.025
M
L
DIM A A1 B C D E G H L M
A1 Y
S
-T-
SEATING PLANE
C M
TX
S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCV7708/D

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